It is known to provide domino logic in which precharged nodes are discharged in response to combinations of input signals. These nodes generate signals which go onto control the discharge of other nodes. Domino logic has become less widely used in recent times due to a variety of factors including the rapid advance in process technology coupled with continuous improvements in design automation that are better suited to logic designs different to domino logic designs. While domino logic is inherently well suited to high speed operation, this advantage has been reduced compared to standard CMOS logic. However, it is primarily the fundamental design complexity and the necessary compromises between robustness and speed which makes the use of domino logic difficult in small process geometries. In particular, noise, charge-sharing, leakage and variability, all of which tend to become greater in significance at smaller process geometries, combine to make the practical use of domino logic in small process geometries difficult. In particular, errors can arise through sources such as late (rising) signals, noise triggering incorrect discharge of domino nodes, inappropriately selected or controlled keeper strength and/or incorrectly controlled or adjusted precharge settings.